The QS7001 Architecture is based on SEALSQ’s Secure RISC-V core which offers high performance and very low power consumption. The QS7001 features a ROM memory dedicated to the storage of low-level drivers, wear leveling and cryptographic code. A large flash memory mapped in both data and code space provides a flexible way to store user data and program code. The ad-X4 hardware cryptographic accelerator featured in the QS7001 is dedicated to perform fast encryption or authentication functions, including crypto acceleration for post quantum cryptography.
A powerful and versatile secure open platform with all the latest cryptographic algorithms, including quantum resistant NIST-appointed Kyber & Dilithium, to provide state-of-the-art security to a wide range of applications.
Main Features
- 80MHz 32-bit Secured RISC-V CPU
- 512KByte Flash, 80KB RAM, 4K executable RAM, 128k ROM (Crypto, Wear Leveling)
- 1Mbps I2C, 33MHz SPI (Communication Interface Auto Detect)
- 4 GPIOs
- 3 timers
- 64 bit unique Chip Serial Number
- Crypto accelerators (ECC, RSA, DH, CRC,…)
- RSA (up to 4096), ECC (256/384), AES (128/192/256), SHA2(256/384)-SHA3(256/384)
- 1.62V to 3.6V, -40°C to 105°C Operating Ranges
- QFN32 Package – TPM Compliant Pinout (I2C & SPI)
